Dma Controller Data Packing - Texas Instruments OMAP5910 Reference Manual

DSP DMA
Table 48. DMA Controller Data Packing
140 DSP Subsystem
A DMA channel has the ability to pack and unpack.
Pack: Pack several consecutive element transfers into wider accesses.
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For example, if the element size is 16 bits, the 32-bit-wide SARAM port can
pack two accesses so that 4 bytes at a time are written into the channel
FIFO. Packing effectively reduces the frequency at which that channel
must be serviced by the port service chain. This can reduce overhead and
improve channel throughput in some cases. Packing options are
determined by port access capabilities and element size. Packing at the
source or destination port can be disabled by software control.
Unpack: Split a single element transfer into several byte accesses. This
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occurs when the DMA port size is less than the size of the element type.
For example, when the element size is programmed as 32 bits and the
destination port is 16 bits wide, the transfer write operation is split into two
16-bit write operations.
The value programmed for channel element size determines the width of the
read access at the source port and write access at the destination port. If the
element size is smaller than the source port width and source packing is
enabled, the source port controller receives 4 bytes per service-chain request.
This reduces overhead because four times as much data is written into the
channel FIFO per service-chain cycle. Similarly, if packing is enabled at the
destination port, 4 bytes are written per iteration of the destination port service
chain.
The DMA controller performs packing as shown in Table 48.
Data Type Port Bus Size
8-bit 16-bit
8-bit 32-bit
16-bit 32-bit
Data Packing
Two data values packed into 16 bits
Four data values packed into 32 bits
Two data values packed into 32 bits
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