Power Management; Emulation Considerations; Timing Considerations - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
4.2.8

Power Management

4.2.9

Emulation Considerations

4.2.10

Timing Considerations

4.2.10.1 Hit Time
42 DSP Subsystem
If you want to temporarily halt the I-Cache to reduce power, you can place its
domain in idle mode:
1) Select the idle mode for the I-Cache domain by making CACHEI = 1 in the
idle configuration register (ICR) of the DSP subsystem. Section 12.3.2.8
describes ICR.
2) Execute the IDLE instruction from the DSP core.
When the I-Cache is in its idle mode or is disabled, instruction-fetch requests
are handled by the external memory interface (EMIF).
To wake the I-Cache from its idle mode:
1) Deselect the idle mode by making CACHEI = 0 in ICR.
2) Execute the IDLE instruction.
The software emulator reads the contents of the I-Cache during the debug
mode. The contents of the I-Cache are not modified by emulator read
operations.
If you set or remove a software breakpoint at an instruction during emulation,
the corresponding line in the I-Cache is automatically invalidated.
As the I-Cache fetches and returns 32-bit words requested by the DSP core,
two key time periods affect the speed of the I-Cache: hit time and miss penalty.
The hit time is the time required for the I-Cache to deliver the 32-bit requested
word to the DSP core in the case of a hit (when the word is present in the
I-Cache). The hit time is either 1 or 2 DSP core clock cycles:
An initial request (a request that follows a period of inactivity) has a hit time
-
of 2 cycles.
Subsequent requests have a hit time of 1 cycle if:
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The requests are consecutive (no inactivity in between) and
J
The requests are to sequential addresses
J
Subsequent requests have a hit time of 2 cycles if:
-
The requests are not consecutive or
J
The requests are to non-sequential addresses
J
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