Addressing Units - Texas Instruments OMAP5910 Technical Reference Manual

5.4.2

Addressing Units

5.4.2.1 LCD Addressing
the DMA to the LCD FIFO, the maximum burst length is set to eight. Only near
frame boundaries, in case of nonmultiple frames, are single transfers started;
otherwise, all requests to the source memory are in 8 x 16 burst requests. The
LCD channel priority bit is fixed high (hard-coded LCD channel constant
parameter).
The configuration registers contain top and bottom address registers for the
two frame buffers and a control register that manages the operation mode
(dual or single), the enable bits for the interrupts, and the source port for the
next transfer. It then returns information by setting the status bits in the same
control register. An interrupt can be sent at the end of the transfer of each
frame. This interrupt line is connected to the global nIRQ line of the DMA.
The LCD channel does not contain the same (read) address unit as the generic
channels. This is because the addressing modes used in the LCD channel are
not compliant with the generic modes. The generic channels receive two
instances of the address unit. The LCD channel does not have the write
address unit instantiated because there is no write address to compute; that
is, the read FIFO address is given by the OMAP LCD controller, so there is no
write address.
At the beginning of LCD operation, the LCD channel gives a start address,
which is conventionally called the top address of the current frame buffer. This
address is sent to the relevant memory port via the scheduler. LCD DMA
requests to the memory port are time-multiplexed along with requests from
generic channels, as described in section 5.3.1, Transfers.
a(0) = SA
a(next) = a(current) + 2
a(next) = TF1 if (a(next) = BF2 and DFM) or (a(next) = BF1 and not (DFM))
a(next) = TF2 if a(next) = BF1 and DFM
where:
a(0) is the first address to be computed.
SA is the start address of the transfer, which is always the top address given
for the first frame buffer.
a(current) is the current address of the byte number within the transfer.
a(next) is the next address to be computed.
BF1 is bottom address for frame 1.
LCD Dedicated Channel
System DMA Controller 5-27