Sdram Write Single 32-Bit Word With Burst Stop - Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
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Figure 8.

SDRAM Write Single 32-Bit Word With Burst Stop

ACCESS_REG
ACCESS_GRANT
COMMAND
ADDRESS
DQ
CURRENT_COL
CURRENT_SIZE
DVALID
SAVE_ADD
LAST_DATE
WRITE (burst reduced to 2) is interrupted by a STOP command because no new request is pending.
Note:
SPRU673
ACTV0
WRITE
NA
A
2
B0/R0
B0/C0
D
C0+1 C0+2
C0
C0+1
1
STOP
NA
D
Ignored
0
Memory Interface Traffic Controller
Memory Interfaces
39

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