Tipb Bridge - Texas Instruments OMAP5910 Technical Reference Manual

Hide thumbs Also See for OMAP5910:

Table of Contents

3.5 TIPB Bridge

The TIPB bridge module manages access to peripheral control and data regis-

ters by the DSP CPU, DSP DMA controller, and MPUI via two peripheral buses

(see Figure 3–9):

Private TIPB: peripherals connected here (timers, interrupt handler)

cannot be accessed by the MPU via the MPUI.

Public TIPB: peripherals connected here (McBSP1, McBSP2, MCSI1,

MCSI2, Mailbox, GPIO UART1-3) can be accessed by the MPU via the

See Chapters 8 and 9 for details on DSP private and public peripherals.

The TIPB bridge consists of two components:

The private TIPB bridge provides a preconfigured bus interface to periph-

erals residing on the the DSP private TIPB.

The public TIPB bridge provides a user-configurable interface to peripher-

als on the DSP public TIPB. It includes functions to tailor the interface

timing to the complement of peripherals operating at a given time.

The TIPB bridge also contains registers to control and monitor the DSP sub-

system idle state. The DSP TIPB bridge may be configured using the following

registers in DSP I/O space:

Control mode register (CMR): DSP I/O word address is 0x0000.

Idle control register (ICR): DSP I/O word address is 0x0001.

Idle status register (ISTR): DSP I/O word address is 0x0002.

DSP Subsystem