Latency In Dma Transfers - Texas Instruments OMAP5910 Reference Manual

7.2.18

Latency in DMA Transfers

SPRU890A
Each element transfer in a channel is composed of a read access (a transfer
from the source location to the channel buffer) and a write access (a transfer
from the channel buffer to the destination location). The time to complete this
activity depends on factors such as:
The selected frequency of the DSP core clock signal. This signal, as
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propagated to the DMA controller, determines the timing for all DMA
transfers.
Wait states or other extra cycles added by or resulting from an interface.
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Activity on other channels. As channels are serviced in a sequential order,
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the number of pending DMA service requests in the other channels affects
how often a given channel can be serviced. For more details on how the
channels are serviced, see section 7.2.6.
Competition from the Microprocessor Port Interface (MPUI). If the MPUI
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is sharing internal RAM with the channels, the DMA controller allocates
cycles to the MPUI like it does to channels. If the MPUI is given exclusive
access to the internal RAM, no channels can access the internal RAM until
the MPUI access configuration is changed (see section 7.2.5).
Competition from the DSP core. If the DMA controller and the DSP core
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request access to the same internal memory block in the same cycle and
the memory block cannot service both requests at the same time, the DSP
core request has higher priority. The DMA request is serviced as soon as
there are no pending DSP core requests.
The timing of synchronization events (if the channel is synchronized). The
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DMA controller cannot service a synchronized channel until the
synchronization event has occurred. For more details on synchronization,
see section 7.2.12.
The minimum (best-case) latency is determined by the ports used. On the
SARAM and DARAM ports, the DMA controller can initiate one access per
cycle, if the DMA controller is not competing with the DSP core for access to
the same memory block. SARAM memory can support one access per cycle
per memory block from either the DMA controller or the DSP core. A DSP core
access to the same SARAM block used by the DMA controller (in the same
cycle) will cause stalls on the DMA access. DARAM memory can support two
accesses per cycle per memory block. If more than two DSP core accesses
are pending to the same DARAM block used by the DMA controller, this
causes stalls on the DMA access. The best-case transfer rate for channels
using these ports would be one cycle to read at the source and one cycle to
write at the destination. External memory accesses through the EMIF port are
handled by the traffic controller; therefore, the minimum latency of the EMIF
port is determined by factors such as pending traffic controller accesses, and
EMIFF and EMIFS configurations. The minimum latency for the peripheral port
is approximately 5 cycles per access.
DSP DMA
DSP Subsystem 159