Mask Interrupt Register (Mir); Interrupt Input Register (Itr) - Texas Instruments OMAP5910 Technical Reference Manual

Interrupt Handler Level 1 and Level 2 Registers
Table 6–18. Interrupt Input Register(ITR)
Bit Name
31 IRQ_31
30–0 IRQ_30–IRQ_0
Table 6–19. Mask Interrupt Register (MIR)
Bit Name
31 IRQ_31_MSK
30–0 IRQ_30_MSK–
IRQ_0_MSK
Table 6–20. Binary-Coded Source IRQ Register (SIR_IRQ_CODE)
Bit Name
4–0 IRQ_NUM
6-22
Description
Interrupt request—1 indicates that the peripheral occupying the
IRQ_31 address space has requested interrupt service from the
MPU.
An edge-triggered interrupt is stored in this register as an
incoming interrupt. When the MPU reads the SIR_IRQ_CODE or
the SIR_FIQ_CODE register, the bit corresponding to the
pending interrupt is reset.
The MPU can also individually clear each bit by writing a 0 to that
bit. (Writing a 1 to the bit does not change the previous state.
This can be used just before the MPU unmasks some interrupts
to ignore specific interrupts.
(Same as bit 31)
Description
Interrupt mask bit—1 prevents IRQ_31 from interrupting MPU
program flow.
If the peripheral on IRQ_31 has been configured to request an
interrupt but masked out in this register, the IRQ_31 bit in the IRQ
register is still set on an interrupt event (and can be read by the
MPU) but does not interrupt program flow.
(Same as bit 31)
Description
This register indicates the IRQ interrupt that is currently being
serviced by the MPU. Reading this register clears the
corresponding bit in the ITR register if the interrupt is configured
as edge triggered.
Reset
Value
0
0
Reset
Value
1
1
Reset
Value
0