Power Management - Texas Instruments OMAP5910 Reference Manual

DSP DMA
7.2.16

Power Management

7.2.17 Emulation Considerations
158 DSP Subsystem
In response to a timeout signal, the DMA controller disables the channel
(EN = 0 in DMACCR) and activity in the channel stops. If the corresponding
interrupt enable bit is set (TIMEOUTIE = 1 in DMACICR), the DMA controller
also sets the timeout status bit (TIMEOUT = 1 in DMACSR) and sends the
timeout signal to the DSP core as an interrupt request. The interrupt request
sets the bus-error interrupt (BERRINT) flag bit in the DSP core. The DSP core
can respond to the interrupt request or ignore the interrupt request.
The DSP module is divided into idle domains that can be programmed to be
idle or active. The state of all domains is called the idle configuration. Any idle
configuration that disables the DMA domain stops the DMA clock and,
therefore, stops activity in the DMA controller.
Note:
There is no hardware handshaking to ensure all ongoing transfers are
completed before the DMA controller goes into the idle state. All ongoing
transfers are immediately suspended when the DMA controller is placed in
the idle state.
When the DMA domain is idle, it can be temporarily reactivated without a
change in the idle configuration in the following case. If one of the multichannel
buffered serial ports (McBSPs) needs the DMA controller for a data transfer,
the DMA controller will leave its idle state to perform the data transfer and then
enter its idle state again.
The FREE bit of DMAGCR controls the behavior of the DMA controller when
an emulation breakpoint is encountered. If FREE = 0 (the reset value), a
breakpoint suspends DMA transfers. If FREE = 1, DMA transfers are not
interrupted by a breakpoint.
SPRU890A