Gpio Process; Gpio Interrupt Reset - Texas Instruments OMAP5910 Technical Reference Manual

Figure 7-12. GPIO Process
GPIO_DEBOUNCING_REG
MPUIO_IN(15:0)
MPUIO_OUT
(15:0)
OUTPUT_REG
7.3.5

GPIO Interrupt Reset

GPIO_INT_EDGE_REG
and GPIO MASKIT
Debouncing
time (steps of
31 µs)
31 µ-8 ms
IO_CNTL
The GPIO interrupt (gpios_int) is generated when one event occurs on one
MPU I/O input (see Figure 7-13).
The edge detection and the interrupt generation are done synchronously with
the 32-kHz system clock (clk_32khz).
These events (and consequently the GPIO_INT interrupt) are reset on one
GPIO interrupt register (GPIO_INT) read.
Only the bits that are active after masking are reset.
The GPIO_INT reset is synchronously asserted and synchronously released
with the 32-kHz system clock. The GPIO_INT register read and the 32-kHz-
system clock are resynchronized with the MPU TIPB fixed peripheral clock
(12-MHz clock) free_run_clock.
When the GPIO_INT read occurs:
-
During a high level of the system clock, the release of the reset is done
immediately.
-
During a low level of the system clock, the reset is done on the next high
level of the system clock.
Even the worst case (reset release on the next 32-kHz cycle) supports the
maximum speed of the MPU I/O module (one edge can be detected every two
32-kHz cycles with a debouncing 0).
Interrupt edge
Transition matches
the programmed
edge and not
masked?
CPU read:
INPUT_LATCH
with no debounce
disable of the latch
on the READ of
the
Interrupt mask
GPIO_MASKIT
If yes, then GPIO
interrupt GPIOS_INT
GPIO_INT status
register:
GPIO_INT
MPU Public Peripherals
MPU I/O
TIPB
7-21