Functional Multiplexing Control 6 Register (Func_Mux_Ctrl_6) - Texas Instruments OMAP5910 Technical Reference Manual

Table 6–33. Functional Multiplexing Control 5 Register (FUNC_MUX_CTRL_5) (Continued)
Bits Name
5–3 CONF_CAM_D_5_R
2–0 CONF_CAM_D_6_R
Table 6–34. Functional Multiplexing Control 6 Register (FUNC_MUX_CTRL_6)
Bits Name
31–30 RESERVED
29–27 CONF_GPIO_4_R
26–24 CONF_GPIO_6_R
23–21 CONF_GPIO_7_R
20–18 CONF_GPIO_11_R
Description
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to CAM.D[5] at
reset.
The control for this I/O is forced to 000 at reset
and in compatibility mode.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to CAM.D[6] at
reset.
The control for this I/O is forced to 000 at reset
and in compatibility mode.
Description
Reserved for future expansion. These bits must always
be written as 0.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO4 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO6 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO7 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
These bits control the multiplexing on the OMAP5910
I/O, which defaults to GPIO11 at reset.
The control for this I/O is forced to 000 at reset and
while in compatibility mode.
OMAP5910 Configuration Registers
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MPU Private Peripherals
Reset
Value
0x0
0x0
Reset
Value
0x0
0x0
0x0
0x0
0x0
6-35