Dma Controller - Texas Instruments OMAP5910 Technical Reference Manual

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DMA Controller

3.4 DMA Controller

Key Features of the DMA Controller

Acting in the background of MPU operation, the DSP DMA controller can:

Transfer data among internal memory, external memory, and peripherals

residing on the DSP public peripheral bus

Transfer data between the MPUI and internal memory

Figure 3–7 shows the ports serviced by the DMA controller within the context

of the DSP subsystem.

The DMA controller has the following important features:

Operation independent of the MPU

Four standard ports, one for each data resource: DARAM, SARAM, exter-

nal or shared system memory via DSP EMIF, and peripherals via the

shared TIPB bridge

An auxiliary port to enable certain transfers between the MPUI and

Six logical channels, which allow the DMA controller to keep track of the

context of six independent block transfers plus a seventh logical channel

for MPUI transfers

Bits for assigning each channel a low priority or a high priority.

Event synchronization. DMA transfers in each channel can be made

dependent on the occurrence of selected events.

An interrupt for each channel. Each channel can send an interrupt to the

DSP CPU on completion of certain operational events.

Software-selectable options for updating addresses for the sources and

destinations of data transfers.

The DMA controller performs data transfers between the following source and

destination ports:

Single-access RAM and SARAM port

Dual-access RAM and DARAM port

External memory and EMIF port

TI peripheral bus and PERIPH port

MPUI interface and MPUI port