Emif Fast Interface Sdram Configuration Register - Texas Instruments OMAP5910 Technical Reference Manual

Traffic Controller Memory Interface Registers
Table 4–16. EMIF Fast Interface SDRAM Configuration Register 1
(EMIFF_SDRAM_CONFIG) (Continued)
Bit Field
26 PWD
25–24 SDRAM_
FREQUENCY
23–8 ARCV
7–4 SDRAM_TYPE
3–2 ARE
4-48
Value Description
SDRAM power-down enable. Controls
power-down state of SDRAM interface:
0 SDRAM interface is not powered down.
1 SDRAM interface is powered down.
PWD is one of the prerequisites to meet TC idle.
PWD must be set before the memory interface
can acknowledge a TC idle request.
SDRAM frequency range. Selects one of four
SDRAM timing configurations based on clock
latencies. See Table 4–18.
00 SDF0 (reset value)
01 SDF1
10 SDF2
11 SDF3
Autorefresh counter register value. Sets the
interval between partial refresh requests to the
SDRAM. See Section 4.3.3.4, SDRAM
Autorefresh Initialization, for formula and example.
Set the SDRAM internal organization (see
Table 4–17)
Autorefresh enable. When autorefresh enable is
set, the EMIF generates a REFR request,
depending on the autorefresh counter and the
burst refresh counter. If refresh enable is not set,
the refresh must be done as a RAS only refresh
under CPU control.
00 Autorefresh disable
01 Autorefresh enable
10 Autorefresh by burst of 4 commands
11 Autorefresh by burst of 8 commands
Reset
Access
Value
R/W 0
R/W 00
R/W 0x6188
R/W 0000
R/W 00