Activity Control Register (Control_Reg) - Texas Instruments OMAP5910 Technical Reference Manual

Multichannel Serial Interfaces
Table 9–34. Activity Control Register (CONTROL_REG)
Bit Name
15–3 Reserved
2 Reserved
1 MCSI software reset
0 MCSI clk enable
9-48
Value Description
Reserved bits. These bits
should always be written
as 0.
Reserved bits. These bits
should always be written
as 0.
Asynchronous reset of
MCSI module
0 Disable
1 Enable
Enable clock of MCSI
module
0 Disable
1 Enable
Note:
The software reset is applied as long as the MCSI software reset bit is set
to 1. A software reset disables the MSCI (the MCSI clk enable bit is cleared)
and initializes the status register. It does not modify the other registers.
To clear an interrupt on the MCSI, the DSP must write to the MCSI status regis-
ter with the bit corresponding to the interrupt set to 1. The MCSI status register
has a two-cycle latency when writing into it, so the interrupt line is cleared two
cycles after a write. In order to prevent clearing the interrupt
handler before the interrupt line is cleared, the interrupt routine must be at least
two cycles long.
Hardware
Access Reset
R 0000 0000
0000 0
R/W 0
R/W 0
R/W 0
Software
Reset
0000 0000
0000 0
0
1
0