Memory Map; Device Types Associated With Chip-Select - Texas Instruments OMAP5910 Reference Manual

2

Memory Map

SPRU673
The TC provides each of the four hosts with:
8-/16-/32-bit single access and burst access, except the LCD controller
-
channel. 16- or 32-bit access must start from the 16- or 32-bit boundary
address.
Size adaptation for 8-, 16-, or 32-bit words, with the requirement that
-
address must be aligned on the correct bit boundary. For example, 32-bit
access must be aligned on 32-bit boundary, 16-bit access must be aligned
on 16-bit boundary, and so forth.
Access duration management (wait state insertion) to enable the
-
connection of slow memory devices
Memory control signal generation (chip-select, memory-specific protocol
-
generation)
16-bit burst access for the LCD controller channels
-
Four external chip-selects and a series of internal address decodes are
provided for external and internal memories and for peripherals attached to the
TI peripheral bus (see Table 2). CS0, CS1, CS2, and CS3 each has an address
range of 32M bytes; the external SDRAM space has an address range of 64M
bytes; the internal SRAM space has an address range of 512K bytes.
EMIFS memory spaces corresponding to CS0 and CS3 are swapped if the
MPU_BOOT pin is high during reset. MPU_BOOT pin 11 is multiplexed with
MCBSP3.DR and USBI_SUSP. This multiplex configuration can be changed
after the reset. The state of this pin is reflected in the BM bit field of the EMIF
slow interface configuration register. For details, see Table 13, EMIF Slow
Interface Configuration Register (EMIFS_CONFIG_REG).
Table 2.

Device Types Associated With Chip-Select

CS Device
CS0 External asynchronous RAM, ROM or flash
External synchronous burst flash
CS1 External asynchronous RAM, ROM or flash
External synchronous burst flash
CS2 External asynchronous RAM, ROM, or flash
External synchronous burst flash
CS3 External asynchronous RAM, ROM, or flash
External synchronous burst flash
Memory Interface Traffic Controller
Memory Map
15