Summary Of The I-Cache Registers; Instruction Cache Registers - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
4.6

Instruction Cache Registers

4.6.1 Overview
Table 5.

Summary of the I-Cache Registers

Name Description
GCR Global control register. Use this register to select the number of active
RAM sets.
FLR0 Flush line registers. Use these registers to flush a line from the cache.
FLR1
NWCR N-way control register. Use this register to initialize the logic for the
2-way cache.
RCR1 RAM set 1 control register. Use this register to initialize the logic for
RAM set 1 and to check the corresponding tag-valid flag.
RCR2 RAM set 2 control register. Use this register to initialize the logic for
RAM set 2 and to check the corresponding tag-valid flag.
RTR1 RAM set 1 tag register. Use the register to define the 12-bit tag for
RAM set 1.
RTR2 RAM set 2 tag register. Use this register to define the 12-bit tag for
RAM set 2.
ISR Status register. Use this register to verify that the I-Cache is enabled
before you write to either of the RAM set tag registers.
†
DSP I/O addresses apply to both OMAP5910 and OMAP5912.
48 DSP Subsystem
Control of the I-Cache is maintained through a set of registers within the
I-Cache. These registers are accessible only at addresses in the I/O memory
space of the DSP subsystem.
Note:
Not every function documented in these registers is supported on
OMAP5910 and OMAP5912. The functions not supported are listed in the
section describing each register. Sections 4.3, 4.4, and 4.5 detail the steps
needed to correctly configure and initialize the DSP I-Cache in the three
supported modes of operation.
DSP I/O See
Address † Section
0x1400 4.6.2
0x1401 4.6.3
0x1402
0x1403 4.6.4
0x1405 4.6.5
0x1407 4.6.5
0x1406 4.6.6
0x1408 4.6.6
0x1404 4.6.7
SPRU890A