Ti Operations; Ti925T Configuration Register - Texas Instruments OMAP5910 Technical Reference Manual

2.6.2.5 Context Switch (or PID: Process Identifier) Register
2.6.2.6

TI Operations

Table 2–13. TI Operations
Function
Set TI925T configuration
Read TI925T configuration
Read I_max
Set I_max
Read I_min
Set I_min
Read thread-ID
Set thread-ID
TI925T_status
Wait-for-interrupt
Note: Required for backward code compatibility. Developers must use the wait-for-interrupt described in register 7.
Table 2–14. TI925T Configuration Register
Bit Name
7 S
The PID register is used in Windows CE mode only. The register is used in con-
junction with the fast-context switch hardware support and is only used when
the Windows CE mode bit is enabled. More information is available upon
request.
Register 15 controls specific TI features. Opcode_2 and CRm select the
different available registers or operations.
The wait-for-interrupt is write-only. The cache size is hard-wired and read-only.
The others are read/write registers.
Opcode_2
0b000
0b000
0b000
0b000
0b000
0b000
0b000
0b000
0b000
0b010
All control bits except L (lock enable) and O (OS type) are set to zero upon
reset.
Value Function
Instruction cache streaming disable
0 I-cache is set in streaming mode. This is the default state after reset.
1 I-cache is set in nonstreaming mode.
CRm Rd
0b0001 Value
0b0001 Value
0b0010 Value
0b0010 Value
0b0011 Value
0b0011 Value
0b0100 Value
0b0100 Value
0b1000 Value
0b1000 Ignored
Coprocessor 15
Instruction
MCR p15, 0, Rd, c15, c1, 0
MRC p15, 0, Rd, c15, c1, 0
MRC p15, 0, Rd, c15, c2, 0
MCR p15, 0, Rd, c15, c2, 0
MRC p15, 0, Rd, c15, c3, 0
MCR p15, 0, Rd, c15, c3, 0
MRC p15, 0, Rd, c15, c4, 0
MCR p15, 0, Rd, c15, c4, 0
MRC p15, 0, Rd, c15, c8, 0
MCR p15, 0, Rd , c15, c8,2
MPU Subsystem 2-23