Dsp Core And Internal Bus Designations - Texas Instruments OMAP5910 Technical Reference Manual

3.1.1 DSP Core
Figure 3–3. DSP Core and Internal Bus Designations
Private
TIPB
bridge
Shared
T
I
P
B
bridge
M
P
U
I
Figure 3–3 shows the DSP core.
Trace FIFO
DSP CPU core
plus hardware accelerator
(DCT/IDCT motion estimation
half-pixel interpolation
DMA controller
6 channels, 5 ports
Feedback / test logic
Architecture Overview
C,D,E,F
DMA
EMIF
I-Cache
M
P,B,C,D,E,F
I
F
SARAM
DMA
96K bytes
P,B,C,D,E,F
DARAM
64K bytes
DMA
Instruction
cache
P
3x8K bytes
P,B,C,D
PDROM
32K bytes
DSP Subsystem 3-5