Compatibility Mode Control 0 Register (Comp_Mode_Ctrl_0) - Texas Instruments OMAP5910 Technical Reference Manual

OMAP5910 Configuration Registers
Table 6–30. Compatibility Mode Control 0 Register (COMP_MODE_CTRL_0)
Bits Name
31–16 RESERVED
15–0 CONF_COMPATIBILITY_R
Table 6–31. Functional Multiplexing Control 3 Register (FUNC_MUX_CTRL_3)
Bits Name
31–0 RESERVED
Table 6–32. Functional Multiplexing Control 4 Register (FUNC_MUX_CTRL_4)
Bits Name
31–30 RESERVED
29–27 CONF_CAM_D_7_R
26–24 CONF_CAM_LCLK_R
6-32
Description
Reserved for future expansion. These bits must be
written to 0x0000h when enabling the OMAP5910
configuration registers.
These bits must be written to 0x0000EAEFh to
enable OMAP5910 configuration bits at offset
0x10h and above. Take care to set the
configuration bits at 0x10h and above
appropriately before writing 0x0000EAEFh to this
register.
Description
Reserved for future expansion. These bits must
always be written as 0.
Description
Reserved for future expansion. These bits must
always be written as 0.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to CAM.D[7] at
reset.
The control for this I/O is forced to 000 at reset
and while in compatibility mode.
These bits control the multiplexing on the
OMAP5910 I/O, which defaults to CAM.LCLK at
reset.
The control for this I/O is forced to 000 at reset
and while in compatibility mode.
Reset
R/W
Value
R 0x0000
R/W 0x0000
Reset
R/W Value
R/W 0x0
Reset
R/W
Value
R/W 0x0
R/W 0x0
R/W 0x0