Dma Global Control Register (Dma_Gcr) - Texas Instruments OMAP5910 Technical Reference Manual

Registers
Table 5–10. DMA Controller Registers (Continued)
Name
DMA_LCD_TOP_
F2_L
DMA_LCD_TOP_
F2_U
DMA_LCD_BOT_
F2_L
DMA_LCD_BOT_
F2_U
Table 5–11. DMA Global Control register (DMA_GCR)
Bit Name
15–4 RESERVED
3 AUTOGATING_ON
2 FREE
1–0 RESERVED
5-40
Description
LCD top address for frame buffer 2
lower bits
LCD top address for frame buffer 2
upper bits
LCD bottom address for frame buffer
2 lower bits
LCD bottom address for frame buffer
2 upper bits
Table 5–11 shows the global control register bit descriptions.
Value Description
DMA clock autogating is as follows:
0 Reserved. Do not use this setting.
1 Allows the DMA to dynamically cut off its clocks
according to its activity. This bit should always be
set to 1.
DMA reaction to the suspend signal is as follows:
0 The DMA suspends all the current transfers when
it receives the suspend signal from the processor.
Transfers resume when the processor releases
the suspend signal. The DMA clock must not be
cut off when the DMA is suspended.
1 The DMA continues running when it receives the
suspend signal from the processor (when the
processor is halted for debug by a breakpoint, for
example).
Size
R/W Address
(Bits)
R/W 16 0xFFFEDB0A
R/W 16 0xFFFEDB0C
R/W 16 0xFFFEDB0E
R/W 16 0xFFFEDB10
Reset Value
U
U
U
U
Reset
Type
Value
RW 1
RW 0