Asynchronous Write With We Operation; Emifs Cs Active Widths For Asynchronous Reads/Writes - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
3.2.8

Asynchronous Write With WE Operation

Figure 7.

Asynchronous Write With WE Operation

EMIFS CS Active Widths for Asynchronous Reads/Writes

Table 6.
FCLK CS Active Width Read
DIV (TC Cycles)
/1 1 * (RDWST + 1) + 1
/2 2 * (RDWST + 1) + 2
32 Memory Interface Traffic Controller
The asynchronous write is used for both file flash and burst flash devices.
Figure 7 shows the timing diagram. Burst write operation is not supported.
FLASH.CLK
(internal)
Ò Ò Ò
FLASH.A
Ò Ò Ò
FLASH.ADV
FLASH.CS_[X]
FLASH.WE
Ò Ò Ò Ò Ò Ò
FLASH.D
Ò Ò Ò Ò Ò Ò
The flash device latches the data on the rising edge of FLASH.WE. The
FLASH.WE low pulse duration is programmable for each device through the
WELEN field in the flash configuration register. The number of wait states
between write operations is programmable for each device through the
WRWST field in the EMIFS_C5x_CONFIG register.
The duration from falling FLASH.CS to falling FLASH.WE (shown in Figure 7)
is equal to the programmed value of WRWST + 1, and the duration for which
FLASH.WE is asserted active low is equal to the programmed value of WELEN
+ 1.
The FLASH.CLK signal is not driven inactive low in the asynchronous write
mode.
The chip-select pulse duration equals:
(WRWST + WELEN + 3) X EMIFS_Ref\
Address valid
WRWST = 1 WELEN = 2
Data to Flash
CS Active Width Write
(TC Cycles)
1 * (WRWST + WELEN + 1) + 2
2 * (WRWST + WELEN + 1) + 4
Ò Ò Ò
Ò Ò Ò
Ò Ò Ò
Ò Ò Ò
SPRU673