Ptv Divisors: Watchdog Timer; Watchdog Timer Characteristics - Texas Instruments OMAP5910 Technical Reference Manual

Table 8–14. PTV Divisors: Watchdog Timer
Table 8–15. Watchdog Timer Characteristics
Input Clock t , Clock Period
clk
12 MHz 1167 ns
12 MHz 1167 ns
† The 12-MHz clock is divided by 14.
PTV
0
1
2
3
4
5
6
7
The timer period is defined by:
-
The value of the PTV, which is forced to 7 if the timer is in watchdog mode
-
The value of the load register
The timer interrupts period is:
t =t X (LOAD_TIM + 1) x 2
int clk
where t is the clock period of the input clock.
clk
Table 8–15 shows the characteristics of the watchdog timer for different input
frequencies:
†
LOAD_TIM
0001
FFFF (max interrupt period)
If LOAD_TIM = 0 and AR (auto-reload mode) = 1, the timer is always 0 and can
never decrement. Here the timer interrupt is asserted and stays asserted all
the time. Since the timer interrupts are edge-senditive, only one interrupt is
recognized because there is one initial edge, and then the interrupt is asserted
constantly.
Divisor
2
4
8
16
32
64
128
256
(PTV+1)
t , Timer Interrupt Period, PTV = 7
int
DSP Private Peripherals
Watchdog Timer
597.34 µs
19.57 s
8-11