External Memory Interface Fast Signal List - Texas Instruments OMAP5910 Technical Reference Manual

4.3.3 External Memory Interface Fast
Table 4–6. External Memory Interface Fast Signal List
4.3.3.1 EMIFF Priority Handler
mode is recommended only for 16-bit accesses since the OMAP5910 EMIFS
keeps chip-select and write enable active between the two accesses gener-
ated by one 32-bit access to EMIFS. While nothing prevents the use of 32-bit
accesses in DPRAM interface mode, avoid it if address must be known valid
while write enable is active.
The EMIFF can interface with synchronous DRAM (SDRAM). The interface
directs all the transactions to the SDRAM device. The bus width is 16 bits.
Table 4–6 shows the EMIFF signal list.
Signal Name
SDRAM.A[12:0]
SDRAM.D[15:0]
SDRAM.CLK
SDRAM.BA[1:0]
SDRAM.CKE
SDRAM.RAS
SDRAM.CAS
SDRAM.WE
SDRAM.DQML
SDRAM.DQMU
This memory interface has two software-selectable priority algorithms for
resolving simultaneous access requests: least recently used and dynamic
priority. The priority scheme is shared with the EMIFS and IMIF and is set in
the OMAP5910 configuration
FUNC_MUX_CTRL_0). See Chapter 6, MPU Private Peripherals, for details
on configuration registers.
-
Least recently used
J
A round-robin arbitration scheme. The highest priority requestor is the
one that least recently accessed the memory.
I/O Bus Description
O 12 - 0 SDRAM address bus
I/O 15 - 0 Data from SDRAM
I/O – Clock to SDRAM
O 1 - 0 SDRAM bank select
O – SDRAM clock enable
O – SDRAM RAS
O – SDRAM CAS
O – SDRAM write enable
O – Lower byte 3-state
O – Upper byte 3-state
registers
Memory Interface Traffic Controller
Memory Interfaces
(bit 20, LRU_SEL in
4-25