Fac Control And Configuration Register (Ctrl); Fac Status Register (Status) - Texas Instruments OMAP5910 Technical Reference Manual

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Frame Adjustment Counter

Table 7–149. FAC Control and Configuration Register (CTRL)

Table 7–150. FAC Status Register (STATUS)

The control and configuration register (CTRL) is a read/write register used to

configure the module. The RUN bit is used to enable the frame-start counter.

If this bit is set to 0, the frame-start counting is disabled immediately. The soft-

ware can use this bit as a software reset for the FAC module by setting the RUN

bit to zero. When the RUN bit is set to zero, the frame-start counter, the

frame-synchronization counter, and the FSC register are reset to zero. The

software reset also clears the status register FSC_FULL bit to zero. If an inter-

rupt has been generated and the FAC module is waiting for an FSC register

read, a software reset puts the counter control back to idle state. This means

that after the software reset the counter starts counting again, regardless of

whether the FSC register has been read or not.

When this bit is set to a 1, an interrupt is generated when FSC is

updated. If this bit is set to a 0, no interrupt is generated. The

INT_ENABLE bit is independent of the CNT bit. The interrupt

can be enabled or disabled in either continuous mode or halt

Enables operation of the counter. When this bit is set to zero,

the frame start counter, the frame-synchronization counter, and

the FSC are reset to zero. Any pending interrupt also is cleared

when RUN is set to zero.

1: Continuous mode: Periodically updates FSC value each time

the frame-adjustment reference count is met.

0: Halt mode: Updates FSC value when the frame-adjustment

reference count is met and halts operation until FSC is read.

The status register (STATUS) is a read/write register that contains an interrupt

This bit is set to a 1 when FSC is updated. This bit is set back to

a 0 when the FSC has been read or RUN bit in control is zero.