Reset Considerations - Texas Instruments OMAP5910 Reference Manual

DSP External Memory Interface
5.2.6

Reset Considerations

5.2.6.1 Effect of Hardware Reset
5.2.6.2 Effect of Software Reset
5.2.7 Power Management
62 DSP Subsystem
The EMIF registers can be reset by hardware and software resets. Section 5.3
details the contents of the EMIF configuration registers after reset.
The EMIF configuration registers are always reset by an OMAP hardware
reset. Section 12.1 describes OMAP hardware resets.
The DSP_RST bit of the ARM_RSTCT1 register controls whether the priority
registers of the TIPB module, the EMIF configuration registers, and the MPUI
control logic (partially) in the DSP subsystem are reset when the DSP_EN bit
(also in ARM_RSTCT1) is cleared. See your device-specific data manual for
more information on ARM_RSTCT1. Clearing the DSP_EN bit always resets
the DSP subsystem. When DSP_RST = 0, clearing the DSP_EN bit resets the
DSP subsystem and also the priority registers, the EMIF configuration
registers, and the MPUI control logic. If DSP_RST = 1, the registers are not
reset.
The DSP_RST bit of the ARM_RST1 register must be set before the DSP
subsystem is taken out of reset.
If you want to temporarily turn off the clock to the EMIF module to reduce
power, you can place its domain in idle mode:
1) Select the idle mode for the EMIF domain by making EMIFI = 1 in the idle
configuration register (ICR) of the DSP subsystem (see section 12.3.2.8).
2) Execute the IDLE instruction in the DSP core.
External memory requests should not be made when the EMIF is in its idle
mode.
To wake the EMIF from its idle mode:
1) Deselect the idle mode by making EMIFI = 0 in ICR.
2) Execute the IDLE instruction.
SPRU890A