Dma Interrupt Control Register (Dmacicr) And Status Register (Dmacsr); Dma Interrupt Control Register (Dmacicr) Fields Descriptions - Texas Instruments OMAP5910 Reference Manual

Figure 85.

DMA Interrupt Control Register (DMACICR) and Status Register (DMACSR)

DMACICR
15
7 6
Reserved
R-0
DMACSR
15
7 6
Reserved SYNC
R-0 R-0
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Table 64. DMA Interrupt Control Register (DMACICR) Fields Descriptions
Bits Field
15−6 Reserved
5 BLOCKIE
4 LASTIE
SPRU890A
Reserved
R-0
5 4
BLOCKIE LASTIE
RW-0 RW-0
Reserved
R-0
5 4
BLOCK LAST
R-0 R-0
Value Description
These read-only bits returns 0s when read.
Whole block interrupt enable bit. BLOCKIE determines how the DMA
controller responds when all of the current block has been transferred
from the source port to the destination port.
0 Do not record the event.
1 Set the BLOCK bit and send the channel interrupt request to the DSP
core.
Last frame interrupt enable bit. LASTIE determines how the DMA
controller responds when the DMA controller starts transferring the
last frame from the source port to the destination port.
0 Do not record the event.
1 Set the LAST bit and send the channel interrupt request to the DSP
core.
3 2
FRAMEIE HALFIE
RW-0 RW-0
3 2
FRAME HALF
R-0 R-0
DSP DMA
8
1 0
DROPIE TIMEOUTIE
RW-1 RW-1
8
1 0
DROP TIMEOUT
R-0 R-0
DSP Subsystem 171