Internal Memory Connections In The Dsp Subsystem - Texas Instruments OMAP5910 Reference Manual

Figure 4.

Internal Memory Connections in the DSP Subsystem

P buses
B buses
C buses
D buses
E buses
F bus
SPRU890A
Configurable I-Cache structure
-
The DSP instruction cache (I-Cache) module is a special-purpose, tightly
coupled, RAM-based program memory. The module is designed to
significantly improve DSP core performance by buffering the instructions
most recently fetched from DSP external memory. The entire external
program memory space is cacheable. Section 4 describes the I-Cache in
more detail.
Figure 4 shows the connections between the internal memory blocks and the
buses of the DSP core.
1 block of 32K bytes
PDROM
The DSP core uses the six sets of buses to simultaneously fetch up to 32 bits
of program code and to read up to 48 bits of data from memory (or to write up
to 32 bits of data to memory). To achieve maximum performance from the
architecture, pay close attention to placement of code and data structures
within the on-chip memory resources. For more details, see the TMS320C55x
Programmer's Guide (SPRU376).
12 blocks of 8K bytes
8 blocks of 8K bytes
DARAM
SARAM
DSP Subsystem Memory
A
To
external
memory
I/F
D
DSP Subsystem 27