Mpu Interface - Texas Instruments OMAP5910 Technical Reference Manual

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3.6 MPU Interface

The MPU interface (MPUI) is a 16-bit parallel port that allows the MPU and the

system DMA controller to communicate with the DSP and its peripherals, facili-

tating software downloads and data transfers. The MPUI provides the MPU

with access to the full memory space of the DSP (16M bytes). In addition, the

MPUI allows the MPU to access devices on the DSP public peripheral bus

through duplicate memory-mapped peripheral registers in the MPU address

space. The MPU domain may also access the control registers of the TIPB

bridge module and the CLKM2 configuration registers. The DSP private

peripherals are not accessible via the MPUI.

MPUI transfers are facilitated by an auxiliary channel of the DSP subsystem

DMA controller; however, this dedicated DMA channel is preconfigured and

need not need to be user-configured for MPUI support.

The MPU domain (including TI925T and system DMA) always masters the

transfer operation. It initiates the read or write of DSP memory or peripherals.

The MPU also controls the parameters of the MPUI by configuring the

MPUI_CTRL_REG and the MPUI_DSP_MPUI_CONFIG register. There are

5 additional registers the MPU can read to observe the state of the MPUI:

MPUI_DEBUG_ADDR

MPUI_DEBUG_DATA

MPUI_DEBUG_FLAG

MPUI_STATUS_REG

MPUI_DSP_STATUS_REG

The MPUI port supports four access modes:

Single-access mode, memory (SAM_M): SARAM, DARAM and, external

memory interface are shared between the DSP domain and the MPU

Single-access mode, peripheral (SAM_P): DSP public peripheral bus is

shared between the DSP domain and the MPU domain.

Host-only mode, memory (HOM_M): MPU has exclusive access to DSP

SARAM, but it cannot access other DSP memory resources.

Host-only mode, peripheral (HOM_P): MPU has exclusive access to the

DSP public peripheral bus.

SAM is the normal operating mode in which all the DSP internal memory and

the public peripherals are accessible by the MPUI interface as well as the DSP.

If both the DSP and the MPU controllers (TI925T and/or system DMA) access

MPU Interface

DSP Subsystem