Section Translation - Texas Instruments OMAP5910 Technical Reference Manual

MPU Memory Management Unit
2.7.6.4 Translating Section References
Figure 2–14. Section Translation
31
Table index
31
31
31
Section base address
31
Section base address
2-34
Figure 2–14 illustrates the complete section translation sequence. The access
permissions contained in the level 1 descriptor must be checked before the
physical address is put on the address bus.
Virtual address
20 19
Translation table base
Translation base
18
Translation base
First-level descriptor
20 19
12
Physical address
20 19
Section index
14 13
14 13
Table index
12 11 10 9 8
AP Domain 1
Section index
0
0
12
2 1 0
0 0
5 4 3 2 1 0
C B 1 0
12
0