Interrupt Level Registers (Ilr0 - Texas Instruments OMAP5910 Technical Reference Manual

Interrupt Handlers
Table 8–29. Interrupt Level Registers (ILR0...ILR15)
Bit Name
5–2 PRIORITY
1 SENS_EDGE
0 FIQ
8-24
Value Description
Define the priority level when the corresponding
interrupt is routed to IRQ or FIQ.
0 is the highest priority level.
15 is the lowest priority level.
0 The corresponding interrupt is falling-edge-sensitive.
1 The corresponding interrupt is low-level-sensitive.
0 0: The corresponding interrupt is routed to IRQ.
1 The corresponding interrupt is routed to FIQ.
Note: Since IRQ is not connected, only the FIQ setting
is useful. This bit must be set to 1 for the
corresponding level 2 interrupt to cause a DSP
interrupt.
Note:
Assuming that all interrupts have the same priority level and they are active
at the same at the same moment, the order of servicing is as follows: IRQ_15,
IRQ_N–1, IRQ_N–2, ..., IRQ_0.
Reset
Type Value
R/W 0
R/W 0
R/W 0