Overview - Texas Instruments OMAP5910 Technical Reference Manual

Overview

6.1 Overview
Figure 6–1. MPU Private Peripherals
OMAP5910
32
E
Flash and
16 M
SRAM I
F
memories
S
E
16
M
Memory interface
SDRAM
I
memories Traffic controller (TC)
F
F
I
M
I
F
32
32
SRAM
1.5M bits
JTAG/
emulation
I/F
6-2
Three standard peripherals are attached to and accessible only by the TI925T
RISC processor private bus (TIPB) to provide housekeeping functions for the
operating system (OS) and applications. These peripherals include timers, a
watchdog timer, and interrupt handlers.
The configuration module allows the software to control the different
OMAP5910 modes. The device identification registers allow the software to
read the different OMAP5910 identification codes.
Figure 6–1 shows the OMAP5910 device with the MPU private peripherals
highlighted.
TMS320C55x DSP
(Instruction Cache, SARAM,
DSP DARAM, DMA,
32
H/W accelerators)
MMU
32
MPU Bus
32
32
32
System
DMA
32
controller
MPU Core
16
(TI925T)
(Instruction
Cache, Data
Clock and reset management
Cache, MMU)
LCD
I/F
OSC
ETM9
12 MHz
DSP private
Private peripherals
peripheral bus
16
Interrupt handlers
DSP public (shared) peripheral bus
16
16
MPU
interface
32
MPU
peripheral
32
bridge
32
MPU private peripheral bus
32
MPU private peripherals
Level 1/2 interrupt handlers
OSC Configuration registers
Device identification
Reset External clock
Clock
32 kHz
requests
DSP
Timers (3)
DSP public peripherals
Watchdog timer
Level 1/2
McBSP1
McBSP3
MCSI1
MCSI2
MPU/DSP shared peripherals
TIPB
switch
UART3 IrDA
MPU public peripherals
McBSP2
USB host I/F
MPU public
peripheral bus
USB function I/F
2
I C
µWire
Camera I/F
MPUIO
32-kHz timer
PWT
PWL
Keyboard I/F
MMC/SD
LPG x2
Frame adjustment
counter
Timers (3)
HDQ / 1-WIRE
Watchdog timer
RTC
Mailbox
GPIO I/F
UART1
UART2