Irq Generated On Vsync Falling Edge - Texas Instruments OMAP5910 Technical Reference Manual

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Camera Interface

Interrupt Generator

Figure 7-9. IRQ Generated on VSYNC Falling Edge

DMA Procedure

The clock divider also allows disabling the external clock by setting the

CAMEXCLK_EN bit.

The interrupt generator handles six cases of interrupt:

Data transfer interrupt. One IRQ is generated per word received.

HSYNC rising edge (start of frame)

HSYNC falling edge (end of frame)

VSYNC rising edge (start of image)

VSYNC falling edge (end of image)

FIFO overflow

Each case is registered by activating (high) one of the six interrupt register bits

to indicate the origin of the interrupt. However, the interrupt mask register can

disable the source of the interruption.

Only one line of interrupt is used to ask for a read of the interrupt register. When

the read occurs, the register is automatically reset and the interrupt signal is

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A typical procedure to perform the data transfer by DMA is as follows:

1) Rising edge of VSYNC sends an interrupt to TI925T to alert the system

DMA that a start of image has occurred. The system DMA is programmed

to move one complete image of data then give an interrupt when complete.

2) High level of HSYNC and proper clock edge start the first data transfer

from the camera to the OMAP5910 camera interface. After the first two

pixels of data are received (8 bits x 4 transfers = 32 bits), a DMA request

is made. The system DMA moves the 32-bit data to a predefined SDRAM

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