Pin Control Register Configuration (Dsp_Write(0X0000) => Pcr) - Texas Instruments OMAP5910 Technical Reference Manual

McBSP1
9.3.4.1 Serial Port Control Register Configuration
9.3.4.2 Pin Control Register Configuration
Table 9–5. Pin Control Register Configuration (DSP_Write(0x0000) => PCR)
Bit Config Value
15–14 00b
13 0b
12 0b
11 0b
10 0b
9 0b
8 0b
7 0b
6 0b
5 0b
4 0b
3 0b
2 0b
1 0b
0 0b
9-8
DSP_Write(0x0000) => SPCR1; set up SPCR1 as initial configuration.
This setup is not needed after reset.
DSP_Write(0x0000) => SPCR2; set up SPCR2 as initial configuration.
This set up is not needed after reset.
DSP_Write(0x0000) => PCR; set up PCR as shown in Table 9–5.
Description
Reserved
Set serial port mode for DX, FSX and CLKX pins
Set serial port mode for DR, FSR and CLKR pins
TX frame-synchronization signal derived by external source
RX frame-synchronization signal derived by external source
CLKX set input pin and derived by external source
CLKR set input pin and derived by external source
Sample rate generator input clock mode bit
CLKS pin status (no meaning in
DX pin status
DR pin status
Set FSX polarity as active high
Set FSR polarity as active high
Set CLKX polarity as data driven on rising edge
Set CLKR polarity as data sampled on falling edge
the OMAP5910
device)