Sdram Mode And Extended Mode Register Initialization - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
3.3.3

SDRAM Mode and Extended Mode Register Initialization

36 Memory Interface Traffic Controller
The LCD channel transfer and MPU cache refill use burst transfers from
SDRAM. LCD channel transfer has a higher priority, and its burst length is
always 8 x 16 bits. SDRAM burst transfers are supported for a maximum of 8
x 16 bits, which can be utilized for DSP and MPU cache line fills and system
DMA. The burst length through mode register initialization would be
(EMIFF_MRS[2:0] PGBL=111b)
The SDRAM controller supports:
The self-refresh mode (idle) and auto-refresh (normal operation)
-
Automatic generation of MRS and EMRS commands to the SDRAM by
-
writing to a mirror configuration register within the OMAP5910 device
Burst sizes of 1x8, 1x16, 1x32, and 4x32 for all accesses and 8x16 burst
-
access for LCD.
Burst across page boundary (local address increment coupled with
-
current address register)
To make SDRAM memory accessible, its internal mode register must first be
configured. The MRS register contains the protocol information used to
communicate with the OMAP5910 device (burst size, latency, write burst,
etc.). The EMRS register enables certain low-power characteristics for the
SDRAM.
Writing to the EMIF fast interface SDRAM MRS register (EMIFF_MRS)
-
automatically forces the generation of an MRS command on the pins of
the SDRAM interface. When the command is issued, the content of the
OMAP5910 MRS register is placed on the SDRAM address bus and
latched by the SDRAM into its internal MRS register.
OMAP5910 uses the same EMIF fast interface SDRAM MRS register,
-
combined with a control bit setting, to write EMRS commands to the
SDRAM. When the CONF_MOD_EMRS_CTRL bit field in the
MOD_CONF_CTRL_0 register is set, the OMAP configures SDRAM
banks to write out the EMIFF_MRS register as EMRS commands instead
of MRS commands.
Reading from the EMIF fast interface SDRAM MRS register does not
-
generate any external transactions.
Note:
Typically, SDRAM requires 100 µs to stabilize after power up. Software is
responsible for performing the initial setup of SDRAM. For more information
refer to the SDRAM manufacturer's data sheet.
SPRU673