Mpu Interrupt Handlers - Texas Instruments OMAP5910 Technical Reference Manual

Dual-core
Hide thumbs Also See for OMAP5910:
Table of Contents

Advertisement

MPU Interrupt Handlers

6.4 MPU Interrupt Handlers
6.4.1
MPU Level 1 Interrupt Handler
6-14
The MPU only supports two interrupt sources: IRQ and FIQ. However, the
OMAP5910 has numerous peripherals and DMA channels which provide
interrupts. To allow these numerous interrupts to be supported using just two
interrupt sources, an interrupt handler is used. The interrupt handlers allow up
to 32 individual interrupts to be programmed to assert either IRQ or FIQ and
they allow these interrupt sources to be masked as well as prioritized with rela-
tionship to one another. If any of these unmasked interrupts occur, then either
a FIQ or IRQ interrupt occurs.
The OMAP5910 has two layers of interrupt handlers, as shown in Figure 6–6.
If an unmasked interrupt occurs on the level 2 interrupt handler, it asserts
IRQ_0 of the level 1 interrupt handler. This allows up to 62 interrupt sources
to be supported.
The OMAP5910 device does not support nested interrupts.
The MPU level 1 interrupt handler has 32 interrupt request lines (IRQ_[31:0]).
These interrupts are generated by peripherals such as the timers, camera,
LCD, the system DMA controller, and the DSP. The interrupt handler handles
edge-triggered or level-sensitive interrupts (individually programmable via the
ILRn registers—see Table 6–23). All interrupts are maskable (individually
enabled and disabled via the mask interrupt register (MIR)—see Table 6–19)
with an internal register. The interrupt source information can be read back
from the ITR register (see Table 6–18, Table 6–19, and Table 6–20). Interrupt
priority is also programmable (ILRn registers) to allow flexibility for different
applications (see Table 6–1). The output from the interrupt handler is routed
to one of the two MPU interrupt (IRQ or FIQ—see Figure 6–6) inputs according
to that interrupt ILRn configuration bit.
A clock request mechanism is implemented to wake up and provide a clock
to the interrupt handler when the OMAP5910 device is in one of the sleep
modes.

Advertisement

Table of Contents
loading

Table of Contents