Sdram Write Single Followed By Write Burst 6 On The Same Bank And Different Page - Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
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Memory Interfaces
Figure 17.
SDRAM Write Single Followed by Write Burst 6 on the Same Bank and
Different Page
ACTV0
ACCESS_REG
2
ACCESS_GRANT
COMMAND
ADDRESS
B0/R0
DQ
CURRENT_COL
CURRENT_SIZE
DVALID
SAVE_ADD
LAST_DATE
WRITE (burst reduced to 1) is followed by a WRITE (6) in the same bank but on a different page.
Note:
48
Memory Interface Traffic Controller
WRIT
STOP
DEA
E
C
2
t
= 9
rc
t
= 5
ras
B0/C0
B0/R0
D
C0+1
C0
0
ACTV0
WRIT
E
B0/R5
D
D
C5+1 C5+2 C5+3 C5+4 C5+5
C5
C5+1 C5+2 C5+3 C5+4
4
5
STOP
D
D
D
D
C5+6
C5+5
3
2
1
0
SPRU673

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