Dma Global Control Register (Dmagcr); Dma Global Control Register (Dmagcr) Field Descriptions - Texas Instruments OMAP5910 Reference Manual

7.3.2

DMA Global Control Register (DMAGCR)

Figure 81. DMA Global Control Register (DMAGCR)
15
7
Reserved
†
Always write 1 to this reserved bit.
Note: R - Read, W = Write
Table 60. DMA Global Control Register (DMAGCR) Field Descriptions
Bits Field
15−4 Reserved
3 Reserved
2 FREE
1 MPUI_EXCL
SPRU890A
The global control register (see Figure 81 and Table 60) is a 16-bit read/write
register. Use this I/O-mapped register to set the emulation mode of the DMA
controller (FREE) and to define how the DMA controller treats the host port
interface (MPUI_EXCL and MPUI_PRIO).
4
R-0
Value Description
These read-only bits return 0s when read.
Always write 1 to this reserved bit.
Emulation mode bit. FREE controls the behavior of the DMA controller
when an emulation breakpoint is encountered:
0 A breakpoint suspends DMA transfers.
1 DMA transfers continue uninterrupted when a breakpoint occurs.
MPUI exclusive access bit. MPUI_EXCL determines whether the
Microprocessor Port Interface (MPUI) has exclusive access to the
internal RAM of the DSP.
Note: Regardless of the value of MPUI_EXCL, the MPUI cannot
access the peripheral port.
0 The MPUI shares the internal RAM with the DMA channels. The MPUI
can access any internal and DSP external memory in its address
reach.
1 The MPUI has exclusive access to the internal RAM. If any channels
must access the DARAM port or the SARAM port, activity in these
channels is suspended.
In this MPUI access configuration, the MPUI can only access the
DARAM port and the SARAM port. It cannot access the DSP external
memory port.
Reserved
R-0
3 2
†
Reserved FREE
RW-1 RW-0
DSP DMA
8
1 0
MPUI_EXCL MPUI_PRIO
RW-0 RW-0
DSP Subsystem 161