Tipb (Private) Bridge Registers; Mpu Posted Write - Texas Instruments OMAP5910 Technical Reference Manual

2.10.4 MPU Posted Write

2.10.5 Pipeline Mode
2.10.6 Abort
2.10.7 TIPB Bridge Registers
Table 2–59. TIPB (Private) Bridge Registers
Register Name
TIPB_CNTL
TIPB_BUS_ALLOC
MPU_TIPB_CNTL
ENHANCED_TIPB_CNTL
ADDRESS_DBG
DATA_DEBUG_LOW
DATA_DEBUG_HIGH
DEBUG_CNTR_SIG
The MPU can perform a posted write. When posted write is enabled inside the
ARM_TIPB_CNTL register, data sent by the MPU is buffered in the MPU TIPB
and the MPU can keep going to another access. The bridge takes care of the
access towards the TIPB; hence the MPU is not stalled during the access.
When pipeline mode is enabled in the ENHANCED_TIPB_CNTL register,
incoming signals from MPU and DMA are buffered. Use pipeline mode when
running at a high frequency.
When abort interrupt is enabled in the ENHANCED_TIPB_CNTL register, an
interrupt is sent to the MPU interrupt handler when a TI peripheral read or write
access is aborted or when any TI peripheral access has a size mismatch.
In case of abort or size mismatch, the address and data of the corresponding
access are saved
DATA_DEBUG_LOW, DATA_DEBUG_HIGH, DEBUG_CNTR_SIG.
Table 2–59 and Table 2–60 list the TIPB bridge registers. Table 2–61 through
Table 2–68 describe the register bits.
Descriptions
TIPB control
TIPB bus allocation
MPU TIPB control
Enhanced TIPB control
Debug address
Debug data LSB
Debug data MSB
Debug control signals
in the following
R/W Size
R/W 16 bits
R/W 16 bits
R/W 16 bits
R/W 16 bits
R 16 bits
R 16 bits
R 16 bits
R 16 bits
MPU TI Peripheral Bus Bridges
registers: ADDRESS_DBG,
Reset
Address
Value
FFFE:CA00 0xFF11
FFFE:CA04 0x0009
FFFE:CA08 0x0000
FFFE:CA0C 0xFFFF
FFFE:CA10 0xFFFF
FFFE:CA14 0xFFFF
FFFE:CA18 0xFFFF
FFFE:CA1C 0x00F8
MPU Subsystem 2-67