Fclkdiv Settings And Resulting Emifs Reference Clock - Texas Instruments OMAP5910 Technical Reference Manual

4.3.2.4 EMIFS Memory Timing Control
Table 4–5. FCLKDIV Settings and Resulting EMIFS Reference Clock
In both asynchronous and synchronous modes all EMIFS-to-memory control
signals are referenced to an internal EMIFS reference clock. The internal
EMIFS reference clock is divided from the TC clock by a programmable value
in the FCLKDIV bit field of the EMIFS chip select configuration register
(EMIFS_CSx_CONFIG). This allows the EMIFS to accommodate timing
constraints of slow devices, even with high system clock rate. Table 4–5 shows
valid FCLKDIV settings and resulting EMIFS reference clock values.
FCLKDIV
00
01
10
11
Depending on the chip-select mode configuration, the EMIFS reference clock
can be output at the FLASH.CLK output pin. In asynchronous read and write
modes, EMIFS reference clock is not output and the FLASH.CLK pin remains
low. In synchronous modes, EMIFS reference clock is present at the
FLASH.CLK device pin.
In synchronous modes a selectable retiming feature enables read data to be
latched by a delayed EMIFS reference clock. The retiming feature accounts
for delays through the OMAP5910 input/output pins by feeding back
FLASH.CLK to offer optimum data and clock alignment. You can select the re-
timing mode using the RT bit in the EMIFS chip-select configuration registers.
EMIFS Reference
TC clock/1
TC clock/2
TC clock/4
TC clock/6
Memory Interface Traffic Controller
Memory Interfaces
4-17