Imif Priority Register (Imif_Prio) - Texas Instruments OMAP5910 Technical Reference Manual

Table 4–8. Traffic Controller Registers (Continued)
Name
ENDIANISM
EMIFF_SDRAM_CONFIG_2 EMIF fast interface SDRAM
EMIFS_CFG_DYN_WAIT
Table 4–9. IMIF Priority Register (IMIF_PRIO)
Bit Field
31–0 Reserved
Table 4–10. EMIF Slow Priority Register (EMIFS_PRIO)
Bit Field
31–0 Reserved
Table 4–11. EMIF Fast Priority Register (EMIFF_PRIO)
Bit Field Description
31–0 Reserved Reserved for future expansion. These pins must always be writ-
ten as 0.
Description
Endianism
Location not used
configuration register 2
EMIF slow wait-state
configuration register
Description
Reserved for future expansion. These pins must always
be written as 0.
Description
Reserved for future expansion. These pins must always be
written as 0.
Traffic Controller Memory Interface Registers
R/W Size Address
R/W 32 bits 0xFFFE:CC34
0xFFFE:CC38
R/W 32 bits 0xFFFE:CC3C
R/W 32 bits 0xFFFE:CC40
Memory Interface Traffic Controller
Reset Value
0x0000 0000
0x0000 0003
0x0000 0000
Reset
Access
Value
R All 0s
Reset
Access
Value
R All 0s
Reset
Access
Value
R All 0s
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