Mcbsp2 Pin Descriptions; Mcbsp2 Registers - Texas Instruments OMAP5910 Technical Reference Manual

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Table 7–78. McBSP2 Pin Descriptions

Table 7–79. McBSP2 Registers

Data receive register 2

Data receive register 1

Data transmit register 2

Data transmit register 1

SPCR2 (15:0)

Serial port control register 2

SPCR1 (15:0)

Serial port control register 1

Receive control register 2

Receive control register 1

Transmit control register 2

Transmit control register 1

SRGR2 (15:0)

Sample rate generator register 2

SRGR1 (15:0)

Sample rate generator register 1

Multichannel register 2

Multichannel register 1

Table 7–78 describes the McBSP2 pins. Table 7–79 lists the McBSP2 regis-

ters. Figure 7–44 shows the McBSP2 interface.

The McBSP2 base address is FFFB:1000 (MPU memory map).

I/O Direction

Receive clock

Transmit clock

Receive frame synchronization

Transmit frame synchronization

MPU Public Peripherals