C55X Dsp Architecture - Texas Instruments OMAP5910 Technical Reference Manual

TMS320C55x DSP CPU Overview
Figure 3–4. C55x DSP Architecture
Data read address buses bb, cb, db (3 x 16)
Data read address buses
BAB, CAB, DAB (3 x 24)
Program address bus PAB (24)
TMS320C55x DSP
Instruction buffer
queue
(64 x 8 bit)
Program
read
bus PB
32
Instruction decoder
controller
1st
instruction
Data write buses EB, FB (2 x 16)
3-8
Program
counter
48 bits
2nd
Program
instruction
address
generation
Status
registers
Program
flow
Pipeline
protection
unit
Interrupts
For details on CPU architecture and instruction set, see the following documents:
-
TMS320C55x Technical Overview (SPRU393)
-
TMS320C55x DSP CPU Reference Guide (SPRU371)
-
TMS320C5510 DSP Functional Overview (SPRU312) (only CPU sections
apply to the OMAP5910 device)
Auxiliary
registers
[0:7]
Data
registers
[0:3]
Ret
Coefficient
A
data
pointer
Smemory/
Xmemory
Ymemory
Cmemory
ALU 16-bit
MAC MAC
AC0 AC1 AC2 AC3
40-bit ALU
Shifter
Transition
registers
Bit
operations