Control Register (Ctrl_Reg) - Offset: X00; Debug Address Register (Debug_Addr) - Offset: X04 - Texas Instruments OMAP5910 Technical Reference Manual

Table 2–49. Control Register (CTRL_REG) – Offset: x00 (Continued)
Bit Value Function
3 1 Enables sending IRQ_ABORT interrupt to the MPU when
an abort condition is indicated by the MPU port from the
DSP system.
0 Disables this interrupt source
2 Reserved
1 1 Enables the time-out feature. An IRQ_ABORT interrupt is
sent to the MPU if a time-out occurs.
0 Disables this interrupt source
0 Frequency mode
0 Low-frequency MPU clock
1 High-frequency MPU clock
Note: In the MPUI, there are three sources which can generate an IRQ_ABORT:
1) Abort from the DSP: This can be masked by setting CTRL_REG[3] to 0.
2) Time-out event occurred: This can be masked by setting CTRL_REG[1] to 0. But masking the time-
out interrupt can cause system to wait forever, if DSP never responds to the MPU request.
3) Burst access detected: This cannot be masked.
These interrupt sources are assigned to the IRQ_ABORT line of the level 1 MPU interrupt handler. The
DEBUG_FLAG register contains the information related to which one of these three sources caused
the interrupt.
Apart from the MPUI, there are other modules such as the TIPB Bridge which can also generate the
IRQ_ABORT interrupt.
Table 2–50. Debug Address Register (DEBUG_ADDR) – Offset: x04
Bit Function
31–24 Reserved
23–0 Bits of address bus from MPU/DMA interface. Saved on abort or
access mismatch.
MPU Interface
Value at
Hardware
Size Access Reset
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Value at
Hardware
Size Access Reset
8 R 0x00
24 R 0xFF FFFF
MPU Subsystem
1
1
1
1
1
1
2-59