Dma Status Register (Dmacsr) Field Descriptions - Texas Instruments OMAP5910 Reference Manual

Table 65. DMA Status Register (DMACSR) Field Descriptions
Bits Field
15−7 Reserved
6 SYNC
5 BLOCK
4 LAST
3 FRAME
SPRU890A
Value Description
These read-only bits returns 0s when read.
Synchronization event status bit. The DMA controller updates SYNC
to indicate when the synchronization event for the channel has
occurred or when the synchronized channel has been serviced.
An error occurs if a DMA synchronization event occurs again before
the DMA controller has finished servicing the previous DMA request.
This error is called a synchronization event drop. You can track this
type of error using the DROPIE bit and the DROP bit.
To select a synchronization event for a channel, use the SYNC bits of
DMACCR.
0 The DMA controller has finished servicing the previous access
request.
1 A synchronization event has occurred. In response to the event, the
synchronized channel submits an access request to its source port.
Whole block status bit. The DMA controller only sets BLOCK if
BLOCKIE = 1 in DMACICR and all of the current block has been
transferred from the source port to the destination port.
0 The whole-block event has not occurred yet, or BLOCK has been
cleared.
1 The whole block has been transferred. A channel interrupt request has
been sent to the DSP core.
Last frame status bit. The DMA controller sets LAST only if
LASTIE = 1 in DMACICR and the DMA controller has started
transferring the last frame from the source port to the destination port.
0 The last-frame event has not occurred yet, or LAST has been cleared.
1 The DMA controller has started transferring the last frame. A channel
interrupt request has been sent to the DSP core.
Whole frame status bit. The DMA controller sets FRAME only if
FRAMEIE = 1 in DMACICR and all of the current frame has been
transferred from the source port to the destination port.
0 The whole-frame event has not occurred yet, or FRAME has been
cleared.
1 The whole frame has been transferred. A channel interrupt request
has been sent to the DSP core.
DSP DMA
DSP Subsystem 173