Camera Interface Registers; Clock Control Register (Ctrlclock) - Texas Instruments OMAP5910 Technical Reference Manual

Camera Interface
7.2.1.10 Camera Interface Registers (FFFB:6800)
Table 7-3. Camera Interface Registers
Register
CTRLCLOCK
IT_STATUS
MODE
STATUS
CAMDATA
GPIO
PEAK_COUNTER
Table 7-4. Clock Control Register (CTRLCLOCK)
Bit Name
31-8 RESERVED
7 LCLK_EN
6 DPLL_EN
5 MCLK_EN
7-12
Because the TIPB register read accesses are resynchronized to the camera
interface clock, the MCLK_EN bit must first be set before any camera interface
register reads are performed. Table 7-3 lists the camera interface registers.
Table 7-4 through Table 7-10 describe the individual registers.
Description
Clock control
Interrupt source status
Camera interface mode configuration
Status
Image data
Camera interface GPIO (general-purpose input/
output)
FIFO peak counter
The MCLK_EN bit gates the 12-MHz master clock of the camera interface
to disable the clock when switching between two clock domains or to save
power consumption when the camera module is not used. To clear
PEAK_COUNTER, read all data in FIFO then write PEAK_COUNTER with 0.
Value Function
This field is reserved (unknown value after
reset).
0 Disables
1 Enables incoming CAM.LCLK
0 Disables
1 Enables DPLL source (48 MHz)
0 Disables
1 Enables internal clock of interface
Offset
R/W Size Address
R/W 32 bits 0x00
R 32 bits 0x04
R/W 32 bits 0x08
R 32 bits 0x0C
R 32 bits 0x10
R/W 32 bits 0x14
R/W 32 bits 0x18
Reset
R/W
Value
R/W
R/W
R/W
R/W
0xX
0x0
0x0
0x0