Data/Address Alignment - Texas Instruments OMAP5910 Technical Reference Manual

5.3.4

Data/Address Alignment

5.3.5 Constraint on Channel Configuration Parameters
During a transfer, all the addresses computed by the DMA must be aligned on
the type of data transferred:
-
If the data type is s8 (8 bits scalar data), addresses can have any value.
-
If the data type is s16 (16 bits scalar data), addresses must be aligned on
16-bit word boundary (the least bit of the address is always 0).
-
If the data type is s32 (32 bits scalar data), addresses must be aligned on
32-bit word boundary (the two least bits of the address are always 00).
-
If bursting is enabled, addresses must be aligned on a four-word burst
boundary (128 bits) regardless of data type (the four least-significant bits
of the address are always 0000).
When using the indexed addressing modes (element index and/or frame
index), all the addresses computed must be aligned on the data type.
Failure to adhere to these address alignment requirements could
yield unexpected results. In the case of the four-word bursting
alignment, failure to properly align the addresses could result in a
lockup condition on the DMA channel. To accomplish proper
alignment, programming of the start address, block size, frame
size, and all indexes must be such that the address of every DMA
access is properly aligned (for a burst, this would mean the first
access of the burst).
Verifying this constraint ensures correct DMA operations when transferring
data between ports with different access capabilities as follows:
[SA modulo]/ES = 0,
Where SA is source address and ES is the element size.
Generic Channels
System DMA Controller 5-21