Transmit-Data Register (Tdr); Receive-Data Register (Rdr) - Texas Instruments OMAP5910 Reference Manual

Dual-core processor microwire interface
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MicroWire Interface
Table 1.
MicroWire Registers (Continued)
Register
Description
CSR
Controland status register
SR1
Setup register 1
SR2
Setup register 2
SR3
Setup register 3
SR4
Setup register 4
SR5
Setup register 5
Table 2.

Transmit-Data Register (TDR)

Bits
Field
15−0
TD
Table 3.

Receive-Data Register (RDR)

Bits
Field
15−0
RD
10
MicroWire Interface
Description
Data to transmit
Whatever its size, the word must be aligned on the most significant bit (MSB)
side.
Note:
The MSB (bit 15) is the first transmitted bit.
Description
Received data
Whatever its size, the word is aligned on the least significant bit (LSB) side.
Note:
The LSB (bit 0) is the last received bit.
R/W
Size
Address
R/W
16 bits
FFFB:3000
R/W
16 bits
FFFB:3000
R/W
16 bits
FFFB:3000
R/W
16 bits
FFFB:3000
R/W
16 bits
FFFB:3000
R/W
16 bits
FFFB:3000
Offset
0x04
0x08
0x0C
0x10
0x14
0x18
Reset
Value
Undefined
Reset
Value
Undefined
SPRU686

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