Registers Of The Dma Controller - Texas Instruments OMAP5910 Reference Manual

DSP DMA
7.3 DSP DMA Controller Registers
7.3.1 Overview
Table 59. Registers of the DMA Controller
Name
DMAGCR
DMAGSCR
DMAGTCR
DMACCR
DMACICR
DMACSR
DMACSDP
DMACSSAL
DMACSSAU
DMACDSAL
DMACDSAU
DMACEN
DMACFN
DMACEI/
DMACSEI
DMACFI/
DMACSFI
DMACDEI
DMACDFI
DMACSAC
DMACDAC
160 DSP Subsystem
Table 59 lists the types of registers in the DMA controller. There are three
global control registers (DMAGCR, DMAGSCR, and DMAGTCR) that affect
all channel activity. In addition, for each of the DMA channels, there are
individual channel configuration registers. For the I/O address of each register,
see the data manual for your OMAP device.
Description
Global control register (only one)
Global software compatibility register (only one)
Global timeout control register (only one)
Channel control register (one for each channel)
Interrupt control register (one for each channel)
Status register (one for each channel)
Source and destination parameters register (one for each channel)
Source start address (lower part) register (one for each channel)
Source start address (upper part) register (one for each channel)
Destination start address (lower part) register (one for each channel)
Destination start address (upper part) register (one for each channel)
Element number register (one for each channel)
Frame number register (one for each channel)
Element index register/source element index register
(one for each channel)
Frame index register/source frame index register
(one for each channel)
Destination element index register (one for each channel)
Destination frame index register (one for each channel)
Source address counter register (one for each channel)
Destination address counter register (one for each channel)
See
Section
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.6
7.3.7
7.3.8
7.3.8
7.3.9
7.3.9
7.3.10
7.3.10
7.3.11
7.3.11
7.3.11
7.3.11
7.3.12
7.3.12
SPRU890A