External Memory Interface Slow Signal List - Texas Instruments OMAP5910 Technical Reference Manual

4.3.1.2 IMIF Operation
4.3.2 External Memory Interface Slow
Table 4–4. External Memory Interface Slow Signal List
Signal Name
FLASH.RDY
FLASH.WP
FLASH.CLK
FLASH.RP
FLASH.CS0
FLASH.CS1
†
FLASH.CS2
FLASH.CS3
† FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu-
ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default.
J
The high-priority queue order is:
H
DMA transfer involving LCD channel
H
DSP
H
Local bus
H
DMA transfer involving channels other than LCD channel
-
Fixed priority is a special case of dynamic priority. To create a fixed priority,
all time-out registers must have a value of 0. This way any request made
goes into the high-priority queue after one clock cycle. Then the high-
priority queue provides a fixed priority.
The 192K bytes of internal SRAM are selected by an internal chip select based
on the appropriate address decode. The interface to the SRAM is 32 bits wide
and provides support for single and burst accesses. The SRAM operates at
the frequency of the traffic controller.
The EMIFS interfaces with and handles all transactions to flash memory,
ROM, asynchronous memories, and synchronous burst flash. The interface
can drive up to four devices by assignment to one of four chip-selects. Each
chip-select has a corresponding register to specify the protocol used for the
associated external device.
Table 4–4 shows the EMIFS signal list.
I/O Bus Description
I – Ready/busy signal from device
O – Write protection
I/O – Clock signal for flash device
O – Flash power-down/reset
O – Active-low chip-select for device
O – Active-low chip-select for device
O – Active-low chip-select for device
O – Active-low chip-select for device
Memory Interface Traffic Controller
Memory Interfaces
4-13