Mpu Memory Map - Texas Instruments OMAP5910 Technical Reference Manual

Table 4–3. MPU Memory Map
Device Name
External Slow Memory Interface (Flash)
FLASH CS0
Reserved
FLASH CS1
Reserved
FLASH CS2
Reserved
FLASH CS3
Reserved
External Fast Memory Interface (SDRAM)
SDRAM
Reserved
Internal Memory Interface (SRAM)
Internal RAM
Reserved
DSP MPUI Interface
MPUI Port RAM
MPUI DSP Peripherals I/O Space
DSP Private TIPB Peripherals (Strobe0)
DSP TI peripheral bus
Reserved
DSP CLKM (clock control)
Reserved
† Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.
Start Address End Address
System Memory Address Space
0000:0000 01FF:FFFF
0200:0000 03FF:FFFF
0400:0000 05FF:FFFF
0600:0000 07FF:FFFF
0800:0000 09FF:FFFF
0A00:0000 0BFF:FFFF
0C00:0000 0DFF:FFFF
0E00:0000 0FFF:FFFF
1000:0000 13FF:FFFF
1400:0000 1FFF:FFFF
2000:0000 2002:FFFF
2003:0000 2FFF:FFFF
DSP Processor Address Space
E000:0000 E0FF:FFFF
E100:0000 E101:FFFF
E100:0000 E100:07FF
E100:0800 E100:7FFF
E100:8000 E100:87FF
E100:8800 E100:8FFF
Size in Bytes
32M bytes
32M bytes
32M bytes
32M bytes
64M bytes
192K bytes
16M bytes
128K bytes
2K bytes
30K bytes
2K bytes
2K bytes
Memory Interface Traffic Controller
Memory Map
†
Data Access
8/16/32 R/W
8/16/32 R/W
8/16/32 R/W
8/16/32 R/W
8/16 R/W
8/16/32 R/W
16/32 R/W
16 R/W
16 R/W
16 R/W
4-7