Control Timer Register (Cntl_Timer); Read Timer Register (Read_Tim); Load Timer High Register (Load_Tim_Hi) - Texas Instruments OMAP5910 Technical Reference Manual

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Table 8–5. Control Timer Register (CNTL_TIMER) (Continued)

Table 8–6. Load Timer High Register (LOAD_TIM_HI)

Table 8–7. Load Timer Low Register (LOAD_TIM_LO)

Descriptions

0: Stop timer

With one-shot mode selected (AR = 0), bit is automatically

reset by internal logic when timer equals 0.

The load timer register (LOAD_TIM) is a 32-bit register (see Table 8–6 and

Table 8–7). The data width of the TIPB connected to this peripheral is only 16

bits. Therefore, two 16-bit TIPB write transactions are needed to load the load

timer register (LOAD_TIM).

If the DSP is ready to load the load timer register (LOAD_TIM), it can send a

32-bit write request (with offset address of 04) to the DSPI. The DSPI has the

capability of converting this 32-bit request into two 16-bit TIPB writes on the

This value is loaded when the timer passes through 0 or when it

starts. LOAD_TIM_HI is the same as LOAD_TIM[31:16].

This value is loaded when the timer passes through 0 or when it

starts. LOAD_TIM_LO is the same as LOAD_TIM[15:0].

The read timer register (READ_TIM) is a 32-bit register (see Table 8–8 and

Table 8–9). The data width of the TIPB connected to this peripheral is only 16

bits. So two 16-bit TIPB read transactions are required to read the value of the

read timer register (READ_TIM). Also, note that since the TIPB strobe is com-

pletely asynchronous with the timer_clk, synchronization is done to make sure

that the read timer register (READ_TIM) value is not read while it is being

incremented.

DSP Private Peripherals